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Compact IO™ Isolated HART Analog Output Module
User’s Manual 0300217-03 Rev. A
7-10
Figure 7-5 (Packet Ladder Continued)
Note: The ladder in Figure 7-5 can be found in the project sample file located on our
website at (www.spectrumcontrols.com)
7.2.3 Packet Interval
The delay between two consecutive packets is called the packet interval. The default
time for the packet interval is 500 ms. This delay is controlled by the module.
The user has the ability to reduce the packet interval by utilizing output word 1 (HART
Packet Just Scanned) in the output image. See Table 7-6 (Module Output Table).
Copying the packet number just scanned to output word 1 allows the module to switch to
the next packet before the 500 ms delay expires. See Figure 7-5.
Note: The amount of time saved using this method depends on the scan time of the
ladder and the update time of each individual HART transmitter.
- Compact™ I/O 1
- Isolated HART 1
- Analog Module 1
- Table of Contents 3
- Preface 7
- Conventions 8
- Used in This 8
- Chapter 1 9
- Module Overview 9
- Section 1.3 10
- Hardware 10
- Features 10
- Section 1.4 11
- System 11
- 1.4.1 System Operation 11
- Section 1.5 12
- Module 12
- Operation 12
- Chapter 2 13
- Quick Start for Experienced 13
- Chapter 3 19
- Installation and Wiring 19
- 3.3.3 Remove Power 21
- 3.3.4 Selecting a Location 21
- 3.5.2 Panel Mounting 24
- 3.7.2 Terminal Door Label 26
- 3.7.5 Wiring the Module 27
- 1.1.6 Wiring Diagram 28
- 3.7.7 Calibration 28
- Chapter 4 29
- Configuring the OF4IH for 29
- CompactLogix Using 29
- RSLogix 5000 29
- Section 4.4 36
- Project Tags 36
- Project 37
- Figure 4-11 (Output Tags) 39
- Section 4.5 40
- Sample Project 40
- Chapter 5 43
- Configuring the OF4IH for a 43
- MicroLogix 1500 Using 43
- RSLogix 500 43
- Section 5.3 48
- Using the 48
- Ladder Sample 48
- Chapter 6 53
- Module Data, Status, and 53
- Channel Configuration 53
- Configuration 56
- 6.3.12 Channel X 57
- 6.3.13 Channel X 59
- 6.3.20 Pad (Word 32) 62
- Chapter 7 67
- Enabling and Using HART on 67
- Table 7-1 (HART Packet 0) 71
- Table 7-2 (HART Packet 1) 72
- Figure 7-4 (Packet Ladder) 75
- 7.2.3 Packet Interval 76
- Section 7.3 77
- Sending 77
- Messages 77
- 7.3.3 Processing a Message 79
- Figure 7-6 Sending Message 80
- Figure 7-7 Receiving Message 81
- Figure 7-8a (Message Ladder) 82
- Figure 7-9b 83
- Figure 7-9c 84
- Figure 7-9d 85
- Figure 7-9e 86
- Figure 7-9f 87
- Figure 7-9g 88
- Figure 7-9h 89
- Figure 7-9i 90
- Figure 7-9j 91
- Figure 7-9k 92
- Figure 7-9l 93
- Figure 7-11b 102
- Figure 7-11c 103
- Figure 7-11d 104
- Figure 7-11e 105
- Section 7.5 107
- HART Protocol 107
- Overview 107
- 7.5.1 Message Format 107
- Attention 113
- Figure 8-7b 115
- 8.2.1 MAIN Routine 117
- 8.2.2 PACKETS Routine 118
- Figure 8-6b 119
- Figure 8-6c 120
- 8.2.3 MSG_TO_MOD Routine 121
- Figure 8-7c 123
- Figure 8-7d 124
- Figure 8-7e 125
- Figure 8-7f 126
- Figure 8-7g 127
- Figure 8-7h 128
- Figure 8-7i 129
- Figure 8-7j 130
- Figure 8-7k 131
- Figure 8-7l 132
- Figure 8-7m 133
- Figure 8-7n 134
- Figure 8-7o 135
- Figure 8-7p 136
- Figure 8-7q 137
- 8.2.4 SRC_CHECK Routine 138
- Figure 8-8b 139
- 8.2.5 DEST_CHECKSUM Routine 140
- Figure 8-9b 141
- 8.2.6 HART_MSG Routine 142
- Figure 8-10b 143
- Figure 8-10c 144
- Figure 8-10d 145
- Figure 8-10e 146
- Figure 8-10f 147
- Figure 8-10g 148
- Figure 8-10h 149
- Figure 8-10i 150
- Figure 8-10j 151
- Figure 8-10k 152
- 8.2.7 WORD_BYTE Routine 153
- Figure 8-11b 154
- Figure 8-11c 155
- 8.2.8 HART_CHECK Routine 156
- Figure 8-12b 157
- 8.2.9 BYTE_WORD Routine 158
- Chapter 9 161
- Diagnostics and 161
- Troubleshooting 161
- 1514131211109876543210 163
- 0000000000000000 163
- Section 9.7 165
- Error Codes 165
- Section 9.8 165
- Inhibit Function 165
- Appendix A 167
- Module Specifications 167
- 0C < Ta < 60C 168
- DEMKO 11 ATEX 1103437X 168
- IIC T4 Gc 168
- Appendix B 169
- HART Universal and Common 169
- Practice Commands 169
- Getting Technical 175
- Assistance 175
- Declaration of 175
- Conformity 175
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